A. Field of the Invention
This invention relates to the field of electronic solid state timing devices.
B. Prior Art
Electronic solid state timing devices are well known which have a high frequency clock source providing a timing reference signal which excites a chain of series connected counters. The first counter of such a series chain divides the high frequency clock reference so as to provide a 1 Hz signal. This signal then drives a divide-by-60 counter to count minutes, followed by a divide-by-12 counter to count hours, followed by serially connected counters to count days and months. Each of these binary counters contains timing intelligence data which must be conveyed to a mode-shared display capable of being commanded to display alternately the day and month or upon receipt of an alternative control command, to display hours and minutes on the same display means. Such display means are normally of the LED or LCD type.
The application of this timing data from the counter elements to a decoder and display is normally accomplished by some means of solid state switching or multiplexing. In the prior art of CMOS multiplexing technology, four CMOS devices, namely two P-channel transistors and two N- channel transistors were used to channel each timing data signal, as a function of the applied control command signals, to the responding display means. In the timing chains of counters, each timing parameter (seconds, minutes, hours, days, months, etc) has been processed using four to six binary digits thereby constituting a plurality of approximately 30 data signals required to be routed and translated to decimal format. Each signal has required a multiplexer transmission gate to permit or inhibit transmission of the data from the counter elements to the decoder input terminals. Each of these transmission gates has been individually activated by control signals. Therefore, the increased complexity of each individual transmission gate incurs a serious penalty in terms of integrated circuit area required to accommodate the necessary transistors and the associated bussing structure and fabrication of capacitance essential to proper counting chain operation.
The complexity of the multiplexing topology exhibited in the CMOS prior art introduces severe penalties in terms of the large magnitude of devices required to perform the necessary counting, data signal routing, switching the heavy plurality of metalization paths in the bussing structure and the excessive quiescent power required for operation and display update. In addition, the prior multiplexer art has required the introduction of a plurality of guard bands between P-channel transistor and N-channel transistor devices to provide electrical isolation. Substantial chip area is thereby required with subsequent performance penalties in other operational modes.
An object of the present invention is a multiplexer which provides 50% hardware savings as compared to the prior art with significant improvements in the reduction of and utilization of chip area, reduced quiescent power drain, ease of fabrication, simplicity of operation and improved overall device reliability.